Delay locked loops (DLLs) are used in integrated circuits for removing phase differences between clock signals, such as phase differences caused by propagation delay. For example, DLLs are often used in clock trees for aligning the phase of an input reference clock with the phase of an output of the clock tree.
A typical DLL includes a phase detector, a charge pump, a loop filter and a voltage-controlled delay line. The phase detector detects a phase difference between a reference clock signal and a feedback clock signal. The phase detector generates a phase control signal as a function of the phase difference and applies the phase control signal to the charge pump, which increases, decreases or does not change a voltage across the loop filter. The loop filter voltage is applied to the voltage-controlled delay line for controlling the propagation delay through the delay line. The reference clock is fed through the delay line to generate an output clock, which is fed back to the phase detector as the feedback clock. The delay line advances or retards the phase of the output clock until the phase of the feedback clock matches the phase of the reference clock. The DLL has then locked the output clock signal onto the phase of the reference clock signal.
Once an integrated circuit having an embedded DLL has been fabricated, the operation of the DLL is tested for fabrication faults and changes in operating characteristics due to variations in process, supply voltage and temperature, which are known as “PVT”. Fabrication faults can affect the functionality of a DLL. Similarly, the phase margin of a DLL can vary as much as a factor of two or more from one integrated circuit to the next due to variations in PVT. Variations in the phase margin that exceed specified margins can lead to difficulties in clock synchronization and other functions commonly performed by DLLs.
An embedded DLL is tested by applying a test clock signal to the reference input of the DLL and then measuring the resulting frequency at the output of the DLL. However, a DLL normally requires that the test clock signal be within the DLL's “locking range” in order to lock the output clock signal onto the phase of the test clock signal. As the operating frequencies of DLLs continue to increase, it is becoming more difficult to provide a DLL with a test clock signal that is within the locking range. For example, the operating frequency of a DLL may be 300-500 MHz while the desired testing frequency may be 30 MHz. Therefore in order to test a DLL at the desired testing frequency, logic designers have been required to build delay lines, such as large strings of inverters, into the feedback path in order to slow the operating frequency of the DLL. These large strings of inverters consume a relatively large area on the integrated circuit, and it is often difficult to achieve the correct delay. Further, the logic cells used to build the delay line have delays that vary with PVT, which can result in an inaccurate and unreliable test.
Improved test methods and circuits are desired for testing embedded DLLs.